5 #ifndef _RTE_ETH_CTRL_H_ 6 #define _RTE_ETH_CTRL_H_ 34 #define RTE_ETH_FLOW_UNKNOWN 0 35 #define RTE_ETH_FLOW_RAW 1 36 #define RTE_ETH_FLOW_IPV4 2 37 #define RTE_ETH_FLOW_FRAG_IPV4 3 38 #define RTE_ETH_FLOW_NONFRAG_IPV4_TCP 4 39 #define RTE_ETH_FLOW_NONFRAG_IPV4_UDP 5 40 #define RTE_ETH_FLOW_NONFRAG_IPV4_SCTP 6 41 #define RTE_ETH_FLOW_NONFRAG_IPV4_OTHER 7 42 #define RTE_ETH_FLOW_IPV6 8 43 #define RTE_ETH_FLOW_FRAG_IPV6 9 44 #define RTE_ETH_FLOW_NONFRAG_IPV6_TCP 10 45 #define RTE_ETH_FLOW_NONFRAG_IPV6_UDP 11 46 #define RTE_ETH_FLOW_NONFRAG_IPV6_SCTP 12 47 #define RTE_ETH_FLOW_NONFRAG_IPV6_OTHER 13 48 #define RTE_ETH_FLOW_L2_PAYLOAD 14 49 #define RTE_ETH_FLOW_IPV6_EX 15 50 #define RTE_ETH_FLOW_IPV6_TCP_EX 16 51 #define RTE_ETH_FLOW_IPV6_UDP_EX 17 52 #define RTE_ETH_FLOW_PORT 18 54 #define RTE_ETH_FLOW_VXLAN 19 55 #define RTE_ETH_FLOW_GENEVE 20 56 #define RTE_ETH_FLOW_NVGRE 21 57 #define RTE_ETH_FLOW_VXLAN_GPE 22 58 #define RTE_ETH_FLOW_MAX 23 64 RTE_ETH_FILTER_NONE = 0,
65 RTE_ETH_FILTER_MACVLAN,
66 RTE_ETH_FILTER_ETHERTYPE,
67 RTE_ETH_FILTER_FLEXIBLE,
69 RTE_ETH_FILTER_NTUPLE,
70 RTE_ETH_FILTER_TUNNEL,
73 RTE_ETH_FILTER_L2_TUNNEL,
74 RTE_ETH_FILTER_GENERIC,
120 #define RTE_ETHTYPE_FLAGS_MAC 0x0001 121 #define RTE_ETHTYPE_FLAGS_DROP 0x0002 128 struct rte_eth_ethertype_filter { 135 #define RTE_FLEX_FILTER_MAXLEN 128 136 #define RTE_FLEX_FILTER_MASK_SIZE \ 137 (RTE_ALIGN(RTE_FLEX_FILTER_MAXLEN, CHAR_BIT) / CHAR_BIT) 169 #define RTE_NTUPLE_FLAGS_DST_IP 0x0001 170 #define RTE_NTUPLE_FLAGS_SRC_IP 0x0002 171 #define RTE_NTUPLE_FLAGS_DST_PORT 0x0004 172 #define RTE_NTUPLE_FLAGS_SRC_PORT 0x0008 173 #define RTE_NTUPLE_FLAGS_PROTO 0x0010 174 #define RTE_NTUPLE_FLAGS_TCP_FLAG 0x0020 176 #define RTE_5TUPLE_FLAGS ( \ 177 RTE_NTUPLE_FLAGS_DST_IP | \ 178 RTE_NTUPLE_FLAGS_SRC_IP | \ 179 RTE_NTUPLE_FLAGS_DST_PORT | \ 180 RTE_NTUPLE_FLAGS_SRC_PORT | \ 181 RTE_NTUPLE_FLAGS_PROTO) 183 #define RTE_2TUPLE_FLAGS ( \ 184 RTE_NTUPLE_FLAGS_DST_PORT | \ 185 RTE_NTUPLE_FLAGS_PROTO) 187 #define TCP_URG_FLAG 0x20 188 #define TCP_ACK_FLAG 0x10 189 #define TCP_PSH_FLAG 0x08 190 #define TCP_RST_FLAG 0x04 191 #define TCP_SYN_FLAG 0x02 192 #define TCP_FIN_FLAG 0x01 193 #define TCP_FLAG_ALL 0x3F 225 RTE_TUNNEL_TYPE_NONE = 0,
226 RTE_TUNNEL_TYPE_VXLAN,
227 RTE_TUNNEL_TYPE_GENEVE,
228 RTE_TUNNEL_TYPE_TEREDO,
229 RTE_TUNNEL_TYPE_NVGRE,
230 RTE_TUNNEL_TYPE_IP_IN_GRE,
231 RTE_L2_TUNNEL_TYPE_E_TAG,
238 #define ETH_TUNNEL_FILTER_OMAC 0x01 239 #define ETH_TUNNEL_FILTER_OIP 0x02 240 #define ETH_TUNNEL_FILTER_TENID 0x04 241 #define ETH_TUNNEL_FILTER_IMAC 0x08 242 #define ETH_TUNNEL_FILTER_IVLAN 0x10 243 #define ETH_TUNNEL_FILTER_IIP 0x20 245 #define RTE_TUNNEL_FILTER_IMAC_IVLAN (ETH_TUNNEL_FILTER_IMAC | \ 246 ETH_TUNNEL_FILTER_IVLAN) 247 #define RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID (ETH_TUNNEL_FILTER_IMAC | \ 248 ETH_TUNNEL_FILTER_IVLAN | \ 249 ETH_TUNNEL_FILTER_TENID) 250 #define RTE_TUNNEL_FILTER_IMAC_TENID (ETH_TUNNEL_FILTER_IMAC | \ 251 ETH_TUNNEL_FILTER_TENID) 252 #define RTE_TUNNEL_FILTER_OMAC_TENID_IMAC (ETH_TUNNEL_FILTER_OMAC | \ 253 ETH_TUNNEL_FILTER_TENID | \ 254 ETH_TUNNEL_FILTER_IMAC) 277 uint32_t ipv6_addr[4];
290 RTE_ETH_GLOBAL_CFG_TYPE_UNKNOWN = 0,
291 RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN,
292 RTE_ETH_GLOBAL_CFG_TYPE_MAX,
306 #define RTE_ETH_FDIR_MAX_FLEXLEN 16 307 #define RTE_ETH_INSET_SIZE_MAX 128 312 enum rte_eth_input_set_field { 313 RTE_ETH_INPUT_SET_UNKNOWN = 0,
316 RTE_ETH_INPUT_SET_L2_SRC_MAC = 1,
317 RTE_ETH_INPUT_SET_L2_DST_MAC,
318 RTE_ETH_INPUT_SET_L2_OUTER_VLAN,
319 RTE_ETH_INPUT_SET_L2_INNER_VLAN,
320 RTE_ETH_INPUT_SET_L2_ETHERTYPE,
323 RTE_ETH_INPUT_SET_L3_SRC_IP4 = 129,
324 RTE_ETH_INPUT_SET_L3_DST_IP4,
325 RTE_ETH_INPUT_SET_L3_SRC_IP6,
326 RTE_ETH_INPUT_SET_L3_DST_IP6,
327 RTE_ETH_INPUT_SET_L3_IP4_TOS,
328 RTE_ETH_INPUT_SET_L3_IP4_PROTO,
329 RTE_ETH_INPUT_SET_L3_IP6_TC,
330 RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
331 RTE_ETH_INPUT_SET_L3_IP4_TTL,
332 RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
335 RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT = 257,
336 RTE_ETH_INPUT_SET_L4_UDP_DST_PORT,
337 RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT,
338 RTE_ETH_INPUT_SET_L4_TCP_DST_PORT,
339 RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT,
340 RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT,
341 RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
344 RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC = 385,
345 RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_SRC_MAC,
346 RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
347 RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
348 RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY,
351 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD = 641,
352 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
353 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
354 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
355 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
356 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
357 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
358 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
360 RTE_ETH_INPUT_SET_DEFAULT = 65533,
361 RTE_ETH_INPUT_SET_NONE = 65534,
362 RTE_ETH_INPUT_SET_MAX = 65535,
369 RTE_ETH_INPUT_SET_OP_UNKNOWN,
372 RTE_ETH_INPUT_SET_OP_MAX
483 RTE_FDIR_TUNNEL_TYPE_UNKNOWN = 0,
484 RTE_FDIR_TUNNEL_TYPE_NVGRE,
485 RTE_FDIR_TUNNEL_TYPE_VXLAN,
543 RTE_ETH_FDIR_ACCEPT = 0,
545 RTE_ETH_FDIR_PASSTHRU,
611 RTE_ETH_PAYLOAD_UNKNOWN = 0,
616 RTE_ETH_PAYLOAD_MAX = 8,
666 #define UINT64_BIT (CHAR_BIT * sizeof(uint64_t)) 667 #define RTE_FLOW_MASK_ARRAY_SIZE \ 668 (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT64_BIT)/UINT64_BIT) 685 uint64_t flow_types_mask[RTE_FLOW_MASK_ARRAY_SIZE];
727 RTE_ETH_FDIR_FILTER_INFO_TYPE_UNKNOWN = 0,
730 RTE_ETH_FDIR_FILTER_INFO_TYPE_MAX,
757 RTE_ETH_HASH_FILTER_INFO_TYPE_UNKNOWN = 0,
764 RTE_ETH_HASH_FILTER_INFO_TYPE_MAX,
771 RTE_ETH_HASH_FUNCTION_DEFAULT = 0,
774 RTE_ETH_HASH_FUNCTION_MAX,
777 #define RTE_SYM_HASH_MASK_ARRAY_SIZE \ 778 (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT64_BIT)/UINT64_BIT) 791 uint64_t sym_hash_enable_mask[RTE_SYM_HASH_MASK_ARRAY_SIZE];
793 uint64_t valid_bit_mask[RTE_SYM_HASH_MASK_ARRAY_SIZE];
#define RTE_ETH_FDIR_MAX_FLEXLEN
uint32_t flex_payload_unit
rte_eth_fdir_filter_info_type
#define RTE_FLEX_FILTER_MAXLEN
uint32_t max_flex_payload_segment_num
uint32_t max_flex_bitmask_num
uint32_t flex_bitmask_unit
enum rte_mac_filter_type filter_type
uint16_t flex_payload_limit
#define RTE_ETH_INSET_SIZE_MAX
uint8_t mac_addr_byte_mask
#define RTE_FLEX_FILTER_MASK_SIZE
rte_eth_hash_filter_info_type